44

I am having a hard time understanding the following syntax in Verilog:

input  [15:0] a;      // 16-bit input
output [31:0] result; // 32-bit output
assign result = {{16{a[15]}}, {a[15:0]}};

I know the assign statement will wire something up to the result bus using wires and combinational logic, but what's up with the curly braces and 16{a[15]}?

4

2 に答える 2

63

The curly braces mean concatenation, from most significant bit (MSB) on the left down to the least significant bit (LSB) on the right. You are creating a 32-bit bus (result) whose 16 most significant bits consist of 16 copies of bit 15 (the MSB) of the a bus, and whose 16 least significant bits consist of just the a bus (this particular construction is known as sign extension, which is needed e.g. to right-shift a negative number in two's complement form and keep it negative rather than introduce zeros into the MSBits).

For what it's worth, the nested curly braces around a[15:0] are superfluous.

于 2010-01-20T16:06:40.270 に答える
43

マットが言ったように、中括弧は連結用です。余分な中括弧16{a[15]}複製演算子です。これらは、Verilog ドキュメント (Std 1364-2005) の IEEE 規格のセクション「5.1.14 連結」で説明されています。

{16{a[15]}}

と同じです

{ 
   a[15], a[15], a[15], a[15], a[15], a[15], a[15], a[15],
   a[15], a[15], a[15], a[15], a[15], a[15], a[15], a[15]
}

ビットブラスト形式で、

assign result = {{16{a[15]}}, {a[15:0]}};

以下と同じです:

assign result[ 0] = a[ 0];
assign result[ 1] = a[ 1];
assign result[ 2] = a[ 2];
assign result[ 3] = a[ 3];
assign result[ 4] = a[ 4];
assign result[ 5] = a[ 5];
assign result[ 6] = a[ 6];
assign result[ 7] = a[ 7];
assign result[ 8] = a[ 8];
assign result[ 9] = a[ 9];
assign result[10] = a[10];
assign result[11] = a[11];
assign result[12] = a[12];
assign result[13] = a[13];
assign result[14] = a[14];
assign result[15] = a[15];
assign result[16] = a[15];
assign result[17] = a[15];
assign result[18] = a[15];
assign result[19] = a[15];
assign result[20] = a[15];
assign result[21] = a[15];
assign result[22] = a[15];
assign result[23] = a[15];
assign result[24] = a[15];
assign result[25] = a[15];
assign result[26] = a[15];
assign result[27] = a[15];
assign result[28] = a[15];
assign result[29] = a[15];
assign result[30] = a[15];
assign result[31] = a[15];
于 2010-01-20T16:32:36.853 に答える