同じWikiPediaの記事で、TSC の問題について次のように述べられています。
With the advent of multi-core/hyper-threaded CPUs, systems with multiple CPUs, and
hibernating operating systems, the TSC cannot be relied on to provide accurate results
— unless great care is taken to correct the possible flaws: rate of tick and whether
all cores (processors) have identical values in their time-keeping registers. **There
is no promise that the timestamp counters of multiple CPUs on a single motherboard will
be synchronized**. In such cases, programmers can only get reliable results by locking
their code to a single CPU. Even then, the CPU speed may change due to power-saving
measures taken by the OS or BIOS, or the system may be hibernated and later resumed
(resetting the time stamp counter). In those latter cases, to stay relevant, the
counter must be recalibrated periodically (according to the time resolution your
application requires).
つまり、最新のCPUはCPUクロックレートを変更して電力を節約でき、TSC値に影響を与える可能性があります。また、TSC は、カーネルが HALT を実行し、外部割り込みが受信されるまでプロセッサを停止する可能性がある場合などの状況ではインクリメントしません。
the second question is that i have intel xeon i3 processor which has 4 processors &
each having 2 cores then measuring the clock ticks will give the ticks of single
processor or addition of all 4 processors..?
これにより、プロセスが 1 つのプロセッサで時刻を読み取り、2 番目のプロセッサに移動して、最初のプロセッサで読み取った時刻よりも前の時刻に遭遇し、その結果、TSC が不安定な時刻源となる状況が発生する可能性があります。