vhdl - VHDL How to add a std_logic_vector with a std_logic signal together?

Question

I've got

douta   : in    std_logic_vector (3 downto 0);
doutb   : in    std_logic_vector (3 downto 0);
c0  : in    std_logic;
f1  : in    std_logic;
f0  : in    std_logic;
res : out   std_logic_vector (3 downto 0);

I'm trying to build a simple ALU, and one of the functions this ALU provides is when

f1 and f0 both = 1 
res = douta plus b plus c0

so I wrote

f1 = '1' and f0 = '1' then res <= douta + doutb + c0;

but obviously its not gonna work because the datatype of douta and doutb is std_logic_vector where as co is just std_logic

and I got this error when compile

' Error 603 line 34 : Incompatible types for arithmetic operator: LHS=std_logic_vector!18, RHS=std_logic

any idea how I can fix this problem ?

edit: also have tried

f1 = '1' and f0 = '1' then res <= douta + doutb + ("000" & c0);

but still no luck, this time the compiler says

LHS=std_logic_vector!7, RHS=array_1_of_std_logic_3_d_0

Answer 1

Please don't use std_logic_vector if you're going to do arithmetic on them. Use ieee.numeric_std, and use the signed or unsigned types. Then you can just add your '0' or '1' to it.

The workaround of using std_logic_arith.all is a fudge using a non-standard library, which can get you into portability troubles when you change toolchains.

I wrote a more detailed page on this: http://parallelpoints.com/node/3

There was some discussion on this on comp.lang.vhdl here: http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/549e1bbffd35914d/83cc0f19350fc392?hl=en&q=group:comp.lang.vhdl+numeric_std#83cc0f19350fc392 and also in the comp.lang.vhdl FAQ.

Answer 2

c0をstd_logic_vectorに変換できます。VHDLを作ってから久しぶりです...

if f1 = '1' and f0 = '1' then
 if c0 = '1' then
   res <= douta + doutb + "0001";
 else
   res <= douta + doutb;
 end if;
end if;

これはおそらくそれほどパフォーマンスが良くありません。おそらく、シリコンコンパイラはそれを非常に優れたものに合成します。おそらく、c0がベクトルに変更されるように記述してから、3つすべてのdouta、doutb、およびコンバータc0を追加することをお勧めします。別のオプションは、ビットごとに計算を行うことですが、コンパイラは何のためにありますか？

ばかげているように聞こえるかもしれませんが、次のようなヒントを与えると、コンパイラがより良い結果を生成する場合があります（大したことではないこのような小さな例で、試して出力を確認してください）。

if f1 = '1' and f0 = '1' then
 if c0 = '1' then
   res <= douta + doutb + "0001";
 else
   res <= douta + doutb + "0000";
 end if;
end if;

別のアドバイスとして、ifを記述し、結果がやや奇妙な場合は、elseを導入して、未決定の状態を修正します（一部のコンパイラーは、自由度が高すぎると動作が悪くなります！）。しかし、それはすでに2004年に戻ってきた私の経験からです!!!

Answer 3

ああ、私は修正を見つけたと思います、次のライブラリを追加する必要があります

use ieee.std_logic_arith.all;

そして私たちが試したことはうまくいくでしょう:)@jdehaanに感謝します

Answer 4

You don't need to convert the std_logic to a std_logic_vector to do the addition. Just do the addition as is, and make sure that "res" has enough bits to hold the max answer. In this case res needs to be 5 bits wide in order for it to now overflow.

And as a style nit, don't name your input ports "dout". That's bad form. Call them din here, because that's what they are. And in the architecture than instantiates this you connect another component's output port named "dout" to the "din" of this component.