Isim の波形ウィンドウで、内部信号と出力が緑色で初期化済みとして表示されますが、入力もすべて初期化されているにもかかわらず、すべて「UU」と表示されます。2 つの入力のいずれかが 1 の場合は常に 1 を追加しようとしています。コードは警告なしで正常に合成されます。何か案は?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity scoreboard2 is
Port ( clk : in STD_LOGIC;
T1 : in STD_LOGIC;
T2 : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (3 downto 0));
end scoreboard2;
architecture Behavioral of scoreboard2 is
signal output_temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal score1,score2: unsigned(1 downto 0) := "00";
signal score3: unsigned(3 downto 0):= "0000";
begin
proc: process(T1,T2,clk)
begin
if(rising_edge(clk)) then
if(T1 = '1') then
score1 <= score1 + 1;
end if;
if(T2 = '1') then
score2 <= score2 + 1;
end if;
end if;
end process proc;
score3 <= score1 & score2;
output_temp <= STD_LOGIC_VECTOR(score3);
Output <= output_temp;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test6 IS
END test6;
ARCHITECTURE behavior OF test6 IS
COMPONENT scoreboard2
PORT(
clk : IN std_logic;
T1 : IN std_logic;
T2 : IN std_logic;
Output : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '1';
signal T1 : std_logic := '1';
signal T2 : std_logic := '1';
--Outputs
signal Output : std_logic_vector(3 downto 0) := "0000";
signal output_temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal score1,score2: unsigned(1 downto 0) := "00";
signal score3: unsigned(3 downto 0):= "0000";
constant clk_period : time := 10 ns;
BEGIN
uut: scoreboard2 PORT MAP (
clk => clk,
T1 => T1,
T2 => T2,
Output => Output
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
wait for 100 ns;
T1 <= '1';
wait;
end process;
END;