vhdl - DAC2904 を使用して三角波を生成するための vhdl コードが機能しない

Question

私は大学でプロジェクトを行っており、DAC2904と Spartan 3 xc3s5000 ボードを使用して三角波を生成したいと考えています。

そのためのコードを書きましたが、機能していません。

コードまたは私のucfファイルの問題である可能性があるかどうかはわかりません：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;   

entity traingular is
    Port ( 
        clk :     in  std_logic; -- on board clock           
        reset :   in  std_logic;
        dac_clk : out std_logic; -- clk for dac module           
        output :  out std_logic_vector(13 downto 0); -- output to dac   
        wr_dac :  out std_logic    -- pulse given to write pin  of dac ic.
    );
end traingular;

architecture Behavioral of traingular is
    signal counter :   unsigned(3 downto 0);
    signal divide :    std_logic_vector(15 downto 0);
    signal sampling_clk , clk_s  : std_logic;
    signal decade :    std_logic_vector(3 downto 0);

-- decade counter used because on board clk freq is 40 hz
-- so the code written below reduce the freq which is applied to dac module very much

begin
    process(clk, reset)
    begin
        if (reset = '1' ) then
            decade <= (others => '0');
        elsif (clk' event and clk = '1') then
            if (decade = "1010") then 
                decade <= (others => '0');
            else 
                decade <= std_logic_vector(unsigned(decade) + 1);
            end if;
        end if; 
    end process;

    clk_s <= '1' when decade = "1010" else
             '0';

    process(clk_s , reset)
    begin
        if (reset='1') then
            divide <= (others => '0');
        elsif (clk_s'event and clk_s = '1') then
            divide <= std_logic_vector(unsigned(divide) + 1);
        end if;
    end process;          

    sampling_clk <= divide(2);

-- input click is still fast so clock is divided further

    dac_clk <= sampling_clk;

    wr_dac <= sampling_clk;

    process(clk , reset)
    begin

-- code below is for counter which will further feed to dac to produce traingular wave.
        if (reset = '1' ) then
            counter <= (others => '0');
        elsif (clk' event and clk = '1') then
            if (counter = "1010") then 
                counter <= (others => '0');
            else 
                counter <= counter + 1;
            end if;
        end if; 
    end process;

    output <= "0000000000" & std_logic_vector(counter); -- output to dac.

end Behavioral;

では、私のコードの問題点を教えてください。