yosys - Use iopadmap with extra clock port

Question

For some reason I want to map some IO ports in my design to cells. iopadmap provide a good way to do this. I used

iopadmap -inpad IBUF O -widthparam WIDTH -nameparam NAME [my selection rule]

However, when afterwards I use other tools to do timing analysis, it won't analyze these paths since they are neither IO nor constrained by clocks.

My current idea is to add the clock to the cells, to make them just like regular registers. So I added another port CLK to IBUF, but how could I connect the global clock to it? I have multiple IBUF cells, so something like

connect -port t:IBUF CLK top_clock

doesn't work.

Answer 1

通常のアプローチは、IO セルを入力と出力を備えた「パススルー」セルとしてモデル化することです。このようなセルを作成するには、次のようなものを使用します。

iopadmap -inpad IBUF O:I -widthparam WIDTH -nameparam NAME [your selection rule]

ただし、本当にクロック信号を IO セルにルーティングしたい場合は、そのための小さなカスタム パスを作成する必要があります。