4 つの FIFO キューと、FIFO インデックスを検索するブロックを実装しました。空でない FIFO が見つかった場合は、データの末尾を抽出し、それをシリアルに送信します。
これはコードです：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Serialize is
port
(
TX : out std_logic_vector(1 downto 0);
RESET, CLK, We1, We2, We3, We4 : in std_logic;
--
DATA_IN_A, DATA_IN_B, DATA_IN_C, DATA_IN_D : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fifo_full1, fifo_full2, fifo_full3, fifo_full4 : out std_logic;
--
SendPackage : out std_logic
);
end Serialize;
architecture rtl of Serialize is
signal step, nr : integer:=0;
signal enl : std_logic := '0';
signal temp : std_logic_vector(31 downto 0);
--signal txx : std_logic_vector(1 downto 0);
TYPE sr_length IS ARRAY (0 to 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL queue, queue1, queue2, queue3 : sr_length;
signal ptr, ptr1, ptr2, ptr3 : integer:= 0;
-- signal tmp : std_logic_vector(1 downto 0);
signal i_a, i_b : std_logic;
signal q_a, q_b, q_c, q_d : std_logic_vector(31 downto 0);
--signal nr : integer := 0;
begin
process(CLK, RESET, We1, We2, We3, We4, DATA_IN_A, DATA_IN_B, DATA_IN_C, DATA_IN_D) is
--variable step, nr : integer:=0;
--variable enl : std_logic := '0';
--variable temp : std_logic_vector(31 downto 0);
begin
if(RESET = '1') then
SendPackage <= '0';
TX<= "00";
-- busy <= '0';
--step:= 0;
--temp := X"00000000";
--enl := '0';
step<= 1;
temp <= X"00000000";
enl <= '0';
ptr <= 0;
ptr1 <= 0;
ptr2 <= 0;
ptr3 <= 0;
fifo_full1 <= '0';
fifo_full2 <= '0';
fifo_full3 <= '0';
fifo_full4 <= '0';
--nr := 0;
nr <= 0;
for i in 0 to 2 loop
queue(i)<=X"00000000";
queue1(i)<=X"00000000";
queue2(i)<=X"00000000";
queue3(i)<=X"00000000";
end loop;
end if;
if(CLK'event) then
if(CLK = '1')then
--SendPackage <= '0';
if(We1 = '1' or We2 = '1' or We3 = '1' or We4 = '1')then
IF (We1 = '1' and ptr <= 3) THEN
for i in 0 to 2 loop
queue(i + 1) <= queue(i);
end loop;
queue(0) <= DATA_IN_A;
ptr <= ptr+ 1;
END IF;
IF (We2 = '1' and ptr1 <= 3) THEN
for i in 0 to 2 loop
queue1(i + 1) <= queue1(i);
end loop;
queue1(0) <= DATA_IN_B;
ptr1 <= ptr1+ 1;
END IF;
IF (We3 = '1' and ptr2 <= 3) THEN
for i in 0 to 2 loop
queue2(i + 1) <= queue2(i);
end loop;
queue2(0) <= DATA_IN_C;
ptr2 <= ptr2 + 1;
END IF;
IF (We4 = '1' and ptr3 <= 3) THEN
for i in 0 to 2 loop
queue3(i + 1) <= queue3(i);
end loop;
queue3(0) <= DATA_IN_D;
--if(ptr3<=3)then ptr3 <= ptr3 + 1; end if;
ptr3 <= ptr3 + 1;
END IF;
elsif(enl = '1')then
SendPackage <= '0';
--if(step = 0) then step <= step + 1; end if;
if(step = 1) then TX <= temp(1 downto 0); i_b <= '1'; step <= step + 1; end if;
if(step = 2) then TX <= temp(3 downto 2); i_b <= '0'; step <= step + 1; end if; --step <= step + 1;
if(step = 3) then TX <= temp(5 downto 4); step <= step + 1; end if;
if(step = 4) then TX <= temp(7 downto 6); step <= step + 1; end if;
if(step = 5) then TX <= temp(9 downto 8); step <= step + 1; end if;
if(step = 6) then TX <= temp(11 downto 10); step <= step + 1; end if;
if(step = 7) then TX <= temp(13 downto 12); step <= step + 1; end if;
if(step = 8) then TX <= temp(15 downto 14); step <= step + 1; end if;
if(step = 9) then TX <= temp(17 downto 16); step <= step + 1; end if;
if(step = 10) then TX <= temp(19 downto 18); step <= step + 1; end if;
if(step = 11) then TX <= temp(21 downto 20); step <= step + 1; end if;
if(step = 12) then TX <= temp(23 downto 22); step <= step + 1; end if;
if(step = 13) then TX <= temp(25 downto 24); step <= step + 1; end if;
if(step = 14) then TX <= temp(27 downto 26); step <= step + 1; end if;
if(step = 15) then TX <= temp(29 downto 28); step <= step + 1; end if;
if(step = 16) then--mai merg un pas pentru a putea transmite tot pachetul. Daca nu pierd 2 biti
TX <= temp(31 downto 30); step <= step + 1; end if;
if(step = 17) then--dupa inca un pas initializez alta trasmitere
--step := 0;
--temp := X"00000000";
--enl := '0';
step <= 1;
temp <= X"00000000";
enl <= '0';
--step <= step + 1;
end if;
i_a <= '1';
--step <= step + 1;
elsif(enl = '0')then
if(nr = 0)then
if(ptr>=1)then
ptr <= ptr - 1;
--temp := queue(ptr-1);
temp <= queue(ptr-1);
q_a <= queue(ptr-1);
SendPackage <= '1';
enl <= '1';
step <= 1;
--enl := '1';
--step := 0;
TX <= "00";
end if;
nr <= nr + 1;
end if;
if(nr = 1)then
if(ptr1>=1)then
ptr1 <= ptr1 - 1;
temp <= queue1(ptr1-1);
q_b <= queue1(ptr1-1);
--temp := queue1(ptr1-1);
SendPackage <= '1';
enl <= '1';
step <= 1;
--enl := '1';
--step := 0;
TX <= "00";
end if;
nr <= nr + 1;
end if;
if(nr = 2)then
if(ptr2>=1)then
ptr2 <= ptr2 - 1;
--temp := queue2(ptr2-1);
temp <= queue2(ptr2-1);
q_c <= queue2(ptr2-1);
SendPackage <= '1';
enl <= '1';
step <= 1;
--enl := '1';
--step := 0;
TX <= "00";
end if;
nr <= nr + 1;
end if;
if(nr >= 3)then
if(ptr3>=1)then
ptr3 <= ptr3 - 1;
temp <= queue3(ptr3-1);
q_d <= queue3(ptr3-1);
--temp := queue3(ptr3-1);
SendPackage <= '1';
enl <= '1';
step <= 1;
nr <= nr + 1;
-- nr := 0;
--enl := '1';
--step := 0;
TX <= "00";
end if;
nr <= 0;
end if;
--if(nr >= 3 )then nr <= 0; end if;
end if;
else
SendPackage <= '0';
i_a <= '0';
end if;
end if;
if(ptr >= 4)then fifo_full1 <= '1'; else fifo_full1 <= '0'; end if;
if(ptr1 >= 4)then fifo_full2 <= '1'; else fifo_full2 <= '0'; end if;
if(ptr2 >= 4)then fifo_full3 <= '1'; else fifo_full3 <= '0'; end if;
if(ptr3 >= 4)then fifo_full4 <= '1'; else fifo_full4 <= '0'; end if;
end process;
end rtl;
いっぱいではなく、送信が実行されている 1 つのキューにデータを挿入するまでは、問題なく動作します。そのステップは省略されています。そのため、送信は機能しません。独立して活躍してほしい。
元 ：
ステップ: 1 3 4 5 6 7 8 9 10 11 12 ... 17
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Altium Designer Winter 09 で作業 (fpga でシミュレーションおよび実装)