Nios IIにデカルトから極座標へのコンバーターを実装するというVHDLプロジェクトに完全にとらわれているため、助けを求めています。すべてのVHDファイルはエラーなしでコンパイルされますが、Modelsimでブロック全体をシミュレートしたい場合は、次のようになります。
# Loading work.counter(a)
# ** Failure: (vsim-3807) Types do not match between component and entity for port "rn".
# Time: 0 ps Iteration: 0 Instance: /bench_conversor/uut/compt File: C:/Users/Sandjiv/Desktop/test_VHDL/counter.vhd Line: 23
# ** Failure: (vsim-3807) Types do not match between component and entity for port "thetan".
# Time: 0 ps Iteration: 0 Instance: /bench_conversor/uut/compt File: C:/Users/Sandjiv/Desktop/test_VHDL/counter.vhd Line: 24
# Fatal error in file C:/Users/Sandjiv/Desktop/test_VHDL/counter.vhd
# while elaborating region: /bench_conversor/uut/compt
# Load interrupted
これは簡単に見つけられるエラーですが、私は自分のタイプを1000回チェックしましたが、それらはすべて一致しているようです。ここでは、カウンター、会話者（ブロック全体）およびそのベンチのコードに従います。もう一度、それらはすべてコンパイルされますが、Modelsimでのシミュレーションでのみこれらのエラーが発生します。
COUNTER.VHD
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
entity COUNTER is
port ( counter_en : in std_logic; --BESOINS???
rn : out signed(31 downto 0);
thetan : out signed(31 downto 0);
Etheta : out std_logic;
SD : in std_logic;
CLK,RESET : in std_logic);
end COUNTER;
architecture A of COUNTER is
signal theta : signed (31 downto 0);
signal r : signed (31 downto 0);
begin
process(CLK,RESET)
begin -- process
-- activities triggered by asynchronous reset (active high)
if RESET = '1' then
r <= "00000000000000000000000000000000";
theta <= "00000000000000000000000000000000";
Etheta <= '0';
-- activities triggered by rising edge of clock
elsif CLK'event and CLK = '1' then
if counter_en = '1' then
if SD = '1' then
if theta /= "000000000000000000000000000000010" then --VALUE THAT CAN BE CHANGED : THETA_MAX = 4095
Etheta <='0';
if r = "00000000000000000000000000001000" then --VALUE THAT CAN BE CHANGED : RMAX = 2000
r <= "00000000000000000000000000000000";
theta <= theta + "0000000000000000000000000000001";
else
r <= r + "00000000000000000000000000000001";
end if;
else
theta <= "00000000000000000000000000000001";
Etheta <= '1';
end if;
else
theta <= theta;
r <= r;
Etheta <= '0';
end if;
else
r <= "00000000000000000000000000000000";
theta <= "00000000000000000000000000000000";
Etheta <= '0';
end if;
end if;
rn <= r;
thetan <= theta;
end process;
end A;
CONVERSOR.VHD
library IEEE ;
use IEEE.std_logic_1164.ALL ;
use IEEE.std_logic_signed.ALL;
use IEEE.std_logic_arith.ALL;
entity CONVERSOR is
generic
(
DATA_WIDTH : natural := 16384000;
ADDR_WIDTH : natural := 32
);
port(
CLK : in STD_LOGIC ;
RESET_Main : in STD_LOGIC ;
Conversor_en : in STD_LOGIC;
Conversor_end : out STD_LOGIC) ;
end CONVERSOR;
architecture A of CONVERSOR is
component FSM is
port(
Clk : in STD_LOGIC ;
Reset_main : in STD_LOGIC ;
Conversion_en : in STD_LOGIC;
RAM_out : in SIGNED(31 downto 0);
Etheta : in STD_LOGIC;
Reset : out STD_LOGIC ;
WR : out STD_LOGIC ;
SD : out STD_LOGIC ;
counter_en : out STD_LOGIC ;
RAM_in : out SIGNED(31 downto 0)
);
end component;
component SINGLE_PORT_RAM is
port
(
clk : in std_logic;
addr : in integer range 0 to 2**ADDR_WIDTH - 1;
data : in signed((DATA_WIDTH-1) downto 0);
we : in std_logic := '1';
q : out signed((DATA_WIDTH -1) downto 0)
);
end component;
component SINGLE_PORT_ROM is
port
(
clk : in std_logic;
addr : in integer range 0 to 2**ADDR_WIDTH - 1;
q : out signed((DATA_WIDTH -1) downto 0)
);
end component;
component COUNTER is
port (
counter_en : in std_logic;
rn : out signed(31 downto 0);
thetan : out signed(31 downto 0);
Etheta : out std_logic;
SD : in std_logic;
CLK,RESET : in std_logic);
end component;
component ADDRESS is
port (
sin : in signed(31 downto 0); -- sinus from ROM
cos : in signed(31 downto 0); -- cosinus from ROM
r : in signed(31 downto 0);
theta : in signed(31 downto 0); --theta from counting block
SD : in std_logic;
Address : out signed(31 downto 0); -- output
CLK,RESET : in std_logic); -- clock and reset
end component;
signal reset : STD_LOGIC;
signal WR : STD_LOGIC ;
signal SD : STD_LOGIC ;
signal counter_en : STD_LOGIC ;
signal RAM_in : SIGNED(31 downto 0);
signal RAM_out : SIGNED(31 downto 0);
signal SIN : SIGNED(31 downto 0);
signal COS : SIGNED(31 downto 0);
signal r_n : SIGNED(31 downto 0);
signal theta_n : SIGNED(31 downto 0);
signal Etheta : STD_LOGIC ;
signal Adresse : SIGNED(31 downto 0);
begin
compt: COUNTER PORT MAP (
counter_en => counter_en,
rn => r_n,
thetan => theta_n,
Etheta => Etheta,
SD => SD,
CLK => clk,
RESET => reset);
MEM_SIN: SINGLE_PORT_ROM port map (
clk => clk,
addr => conv_integer(theta_n), --SUREMENT PB DE CONVERSION ICI!!
q => SIN
);
MEM_COS: SINGLE_PORT_ROM port map (
clk => clk,
addr => conv_integer(theta_n), --SUREMENT PB DE CONVERSION ICI!!
q => COS
);
calcul_adress: ADDRESS PORT MAP (
sin => sin,
cos =>cos,
r => r_n,
theta => theta_n,
SD => SD,
Address => adresse,
clk => clk,
RESET => Reset
);
--RAM: SINGLE_PORT_RAM port map (
-- clk => clk,
-- addr => conv_integer(adresse),
-- data => RAM_in,
-- we => WR,
-- q => RAM_out
-- );
Machine_etat: FSM port map (
Clk => CLK ,
Reset_main => Reset_main ,
Conversion_en => Conversor_en,
RAM_out => RAM_out,
Etheta => Etheta,
Reset => reset,
WR => WR,
SD => SD,
counter_en => counter_en,
RAM_in => RAM_in
);
end A;
BENCH_CONVERSOR
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
entity bench_conversor is
end bench_conversor;
architecture BEHAVIOR of bench_conversor is
component CONVERSOR
port(
CLK : in STD_LOGIC ;
RESET_Main : in STD_LOGIC ;
Conversor_en : in STD_LOGIC;
Conversor_end : out STD_LOGIC) ;
end component;
-- inputs
signal Conversor_en : std_logic;
signal clk : std_logic;
signal reset_main : std_logic;
-- output
signal Conversor_end : std_logic;
-- clock period definition
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CONVERSOR PORT MAP (
CLK => CLK,
RESET_Main => Reset_main,
Conversor_en => Conversor_en,
Conversor_end => Conversor_end
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process: process
begin
clk <= '0';
wait for clk_period/2; --for 5 ns signal is '0'
clk <= '1';
wait for clk_period/2; --for next 5 ns signal is '1'
end process;
-- stimulus process
stim_process : process
begin
wait for 50 ns;
conversor_en <= '0';
Reset_main <='1';
wait for 50 ns;
conversor_en <= '0';
Reset_main <='1';
wait; -- va attendre pour toujours
end process;
end BEHAVIOR;
ご協力ありがとうございました。