このスレッドを編集して、新しいプロジェクト全体を更新し、読みやすくしました。
--Propagate & generate team--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY PG_team_1bit IS
PORT(a, b:IN STD_LOGIC;
p: OUT STD_LOGIC;
g: OUT STD_LOGIC);
END PG_team_1bit;
ARCHITECTURE PG_team_1bit_arch OF PG_team_1bit IS
BEGIN
p <= a XOR b;
g <= a AND b;
END PG_team_1bit_arch;
--Grey Box--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY Grey_box IS
PORT(P, G, Gminus:IN STD_LOGIC;
NewG: OUT STD_LOGIC);
END Grey_box;
ARCHITECTURE Grey_box_arch OF Grey_box IS
SIGNAL temp: STD_LOGIC;
BEGIN
temp <= P AND Gminus;
NewG <= G OR temp;
END Grey_box_arch;
--Black Box--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY Black_box IS
PORT(P, G, Pminus, Gminus:IN STD_LOGIC;
NewP, NewG: OUT STD_LOGIC);
END Black_box;
ARCHITECTURE Black_box_arch OF Black_box IS
SIGNAL temp: STD_LOGIC;
BEGIN
NewP <= P AND Pminus;
temp <= P AND Gminus;
NewG <= G or temp;
END Black_box_arch;
--Full adder--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY Full_Adder IS
PORT(A, B, Cin:IN STD_LOGIC;
S, Cout: OUT STD_LOGIC);
END Full_Adder;
ARCHITECTURE Full_Adder_arch OF Full_Adder IS
SIGNAL p: STD_LOGIC;
BEGIN
p <= A XOR B;
S <= p XOR Cin;
Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin);
END Full_Adder_arch;
--SKLANSKY SPARSE TREE ADDER 32 bit--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY SSTA32 IS
PORT(A, B:IN STD_LOGIC_VECTOR(31 downto 0);
S: OUT STD_LOGIC_VECTOR(32 downto 0));
END SSTA32;
ARCHITECTURE SSTA32_arch of SSTA32 IS
SIGNAL con: STD_LOGIC;
SIGNAL p: STD_LOGIC_VECTOR(31 downto 0);
SIGNAL g: STD_LOGIC_VECTOR(31 downto 0);
SIGNAL NewGG: STD_LOGIC_VECTOR(6 downto 0);
SIGNAL NewP: STD_LOGIC_VECTOR(6 downto 0);
SIGNAL NewBG: STD_LOGIC_VECTOR(6 downto 0);
variable j : integer := 0;
variable k : integer := 0;
variable l : integer := 0;
variable m : integer := 0;
variable d : integer := 0;
variable e : integer := 0;
COMPONENT PG_team_1bit
PORT(a, b:IN STD_LOGIC;
p: OUT STD_LOGIC;
g: OUT STD_LOGIC);
END COMPONENT;
COMPONENT Grey_box IS
PORT(P, G, Gminus:IN STD_LOGIC;
NewG: OUT STD_LOGIC);
END COMPONENT;
COMPONENT Black_box IS
PORT(P, G, Pminus, Gminus:IN STD_LOGIC;
NewP, NewG: OUT STD_LOGIC);
END COMPONENT;
COMPONENT Full_Adder IS
PORT(A, B, Cin:IN STD_LOGIC;
S, Cout: OUT STD_LOGIC);
END COMPONENT;
BEGIN
con <= '1';
GENERATE_LABEL_1:
FOR i IN 0 TO 31 GENERATE
PG_team_1bit_i: PG_team_1bit PORT MAP(a(i), b(i), p(i), g(i));
END GENERATE GENERATE_LABEL_1;
GENERATE_LABEL_2:
FOR i IN 0 TO 31 GENERATE
BEGIN
F0 : IF ((i=1) OR (i=5) OR (i=9) OR (i=13) OR (i=17) OR (i=21) OR (i=25) OR (i=29)) GENERATE
BEGIN Grey_box_i: Grey_box PORT MAP(p(i), g(i), g(i-1), NewGG(j));--
j := j+1;
END GENERATE F0;
F1 : IF ((i/=1) AND (i/=5) AND (i/=9) AND (i/=13) AND (i/=17) AND (i/=21) AND (i/=25) AND (i/=29)) GENERATE
BEGIN Black_box_i: Black_box PORT MAP(p(i), g(i), p(i-1), g(i-1), NewP(k), NewBG(k));
k := k+1;
END GENERATE F1;
END GENERATE GENERATE_LABEL_2;
GENERATE_LABEL_3:
FOR i IN 0 TO 31 GENERATE
BEGIN
F2 : IF (i=3) GENERATE
BEGIN Grey_box_i: Grey_box PORT MAP(NewP(m), NewBG(m), NewGG(m), DNewG);
m := m+1;
END GENERATE F2;
F3 : IF ((i=7) OR (i=11) OR (i=15) OR (i=19) OR (i=23) OR (i=27) OR (i=31)) GENERATE
BEGIN Black_box_i: Black_box PORT MAP(NewP(m), NewBG(m), con, NewBG(m), TNewP(l), TNewBG(l));
l := l+1;
END GENERATE F3;
END GENERATE GENERATE_LABEL_3;
GENERATE_LABEL_4:
FOR i IN 0 TO 31 GENERATE
BEGIN
F4 : IF (i=3) GENERATE
BEGIN C(d) <= '0';
d := d+1;
C(d) <= NOT DNewG;
d := d+1;
END GENERATE F4;
F5 : IF (i=7) GENERATE
BEGIN Grey_box_i: Grey_box PORT MAP(TNewP(e), TNewBG(e), DNewG, DNewG2);
C(d) <= NOT DNewG2;
d := d+1;
e := e+1;
END GENERATE F5;
F6 : IF (i=11) GENERATE
BEGIN Grey_box_i: Grey_box PORT MAP(NOT TNewP(e), NOT TNewBG(e), DNewG2, C(d));
d := d+1;
e := e+1;
END GENERATE F6;
F7 : IF (i=15) GENERATE
BEGIN Black_box_i: Black_box PORT MAP(TNewP(e), TNewBG(e), TNewP(e-1), TNewBG(e-1), QNewP, QNewBG);
Grey_box_i: Grey_box PORT MAP(QNewP, QNewBG, DNewG2, DNewG3);
C(d) <= DNewG3;
d := d+1;
e := e+1;
END GENERATE F7;
F8 : IF (i=19) GENERATE
BEGIN Grey_box_i: Grey_box PORT MAP(NOT TNewP(e), NOT TNewBG(e), DNewG3, C(d));
d := d+1;
e := e+1;
END GENERATE F8;
F9 : IF (i=23) GENERATE
BEGIN Black_box_i: Black_box PORT MAP(TNewP(e), TNewBG(e), TNewP(e-1), TNewBG(e-1), PNewP, PNewBG);
Grey_box_i: Grey_box PORT MAP(PNewP, PNewBG, DNewG3, C(d));
d <= d+1;
e <= e+1;
END GENERATE F9;
F10 : IF (i=27) GENERATE
BEGIN Black_box_i: Black_box PORT MAP(NOT TNewP(e), NOT TNewBG(e), PNewP, PNewBG, HNewP, HNewBG);
Grey_box_i: Grey_box PORT MAP(HNewP, HNewBG, DNewG3, C(d));
END GENERATE F10;
END GENERATE GENERATE_LABEL_4;
d := 0;
GENERATE_LABEL_5:
FOR i IN 0 TO 31 GENERATE
BEGIN
F11 : IF ((i=0) AND (d=0)) GENERATE
BEGIN Cin <= C(d);
d := d+1;
END GENERATE F11;
F12 : IF ((i=4) AND (d=1)) GENERATE
BEGIN Cin <= C(d);
d := d+1;
END GENERATE F12;
F13 : IF ((i=8) AND (d=2)) GENERATE
BEGIN Cin <= C(d);
d := d+1;
END GENERATE F13;
F14 : IF ((i=12) AND (d=3)) GENERATE
BEGIN Cin <= C(d);
d := d+1;
END GENERATE F14;
F15 : IF ((i=16) AND (d=4)) GENERATE
BEGIN Cin <= C(d);
d := d+1;
END GENERATE F15;
F16 : IF ((i=20) AND (d=5)) GENERATE
BEGIN Cin <= C(d);
d := d+1;
END GENERATE F16;
F17 : IF ((i=24) AND (d=6)) GENERATE
BEGIN Cin <= C(d);
d := d+1;
END GENERATE F17;
F18 : IF ((i=28) AND (d=7)) GENERATE
BEGIN Cin <= C(d);
d := d+1;
END GENERATE F18;
Full_Adder_i: Full_Adder PORT MAP(a(i), b(i), Cin, S(i), Cout);
Cin <= Cout;
F19 : IF (i=31) GENERATE
BEGIN S(32) <= Cout;
END GENERATE F19;
END GENERATE GENERATE_LABEL_5;
END SSTA32_arch;
私が得るエラーは次のとおりです: -私が使用するほとんどすべての信号の静的な信号名ではありません。-変数宣言は、私が行った場所では許可されていません。-不明な識別子。- シグナル代入のターゲットが不正であり、 - 並行ステートメントが不正です。
それらを修正するためのヒントはありますか？また、正しい場合は生成されますか?プロセスを回避するためにそれを変更しました。前もって感謝します