ここに私のVerilogコードからのビットがあります
reg [17:0]FilterCoeffRam[95:0]; // Filter Coefficients
reg [17:0]CoeffRam01[0:5];
reg [17:0]CoeffRam02[0:5];
reg [17:0]CoeffRam03[0:5];
reg [17:0]CoeffRam04[0:5];
reg [17:0]CoeffRam05[0:5];
reg [17:0]CoeffRam06[0:5];
reg [17:0]CoeffRam07[0:5];
reg [17:0]CoeffRam08[0:5];
reg [17:0]CoeffRam09[0:5];
reg [17:0]CoeffRam10[0:5];
reg [17:0]CoeffRam11[0:5];
reg [17:0]CoeffRam12[0:5];
reg [17:0]CoeffRam13[0:5];
reg [17:0]CoeffRam14[0:5];
reg [17:0]CoeffRam15[0:5];
reg [17:0]CoeffRam16[0:5];
integer k;
initial
begin
$readmemh("FilterCoeff96.txt",FilterCoeffRam);
for(k=0; k<6; k=k+1)
begin
CoeffRam01[k]=FilterCoeffRam[k];
CoeffRam02[k]=FilterCoeffRam[k+6];
CoeffRam03[k]=FilterCoeffRam[k+12];
CoeffRam04[k]=FilterCoeffRam[k+18];
CoeffRam05[k]=FilterCoeffRam[k+24];
CoeffRam06[k]=FilterCoeffRam[k+30];
CoeffRam07[k]=FilterCoeffRam[k+36];
CoeffRam08[k]=FilterCoeffRam[k+42];
CoeffRam09[k]=FilterCoeffRam[k+48];
CoeffRam10[k]=FilterCoeffRam[k+54];
CoeffRam11[k]=FilterCoeffRam[k+60];
CoeffRam12[k]=FilterCoeffRam[k+66];
CoeffRam13[k]=FilterCoeffRam[k+72];
CoeffRam14[k]=FilterCoeffRam[k+78];
CoeffRam15[k]=FilterCoeffRam[k+84];
CoeffRam16[k]=FilterCoeffRam[k+90];
end
end
txt ファイルから 96 個の 18 ビット 16 進値を読み取り、それらを FilterCoeffRam レジスタに格納しています。
次に、これらの係数を 16 個のレジスタで均等に分割しています。理想的には、これらの 16 個の 6x18 ビット レジスタを ROM として合成する必要があります。しかし、合成レポートでは、これらは ROM としてではなく、レジスタとしてリストされています。
WARNING:Xst:1780 - Signal <FilterCoeffRam> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1781 - Signal <CoeffRam16> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam15> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam14> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam13> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam12> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam11> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam10> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam09> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam08> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam07> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam06> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam05> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam04> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam03> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam02> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <CoeffRam01> is used but never assigned. Tied to default value.
それらがレジスタではなく ROM として推論されるようにするにはどうすればよいですか