testing - vhdl の同期/非同期 d 型フリップフロップ

Question

VHDL の設定に問題があります。2 つの異なるアーキテクチャで単純な D-TYPE FLIP FLOP を作成する必要があります。1 つは同期で、もう 1 つは非同期である必要があります。エンティティのコードは

entity FD is
Port (  D:  In  std_logic;
    CK: In  std_logic;
    RESET:  In  std_logic;
    Q:  Out std_logic);
end FD;


architecture SYNCH of FD is 

begin
PSYNCH: process(CK,RESET)
begin
  if CK'event and CK='1' then 
    if RESET='1' then 
      Q <= '0'; 
    else
      Q <= D; 
    end if;
  end if;
end process;

end SYNCH;

architecture ASYNCH of FD is 

begin

PASYNCH: process(CK,RESET)
begin
  if RESET='1' then
    Q <= '0';
  elsif CK'event and CK='1' then 
    Q <= D; 
  end if;
end process;

end ASYNCH;


configuration CFG_FD_ASYNCH of FD is
for ASYNCH
end for;
end CFG_FD_ASYNCH;


configuration CFG_FD_SYNCH of FD is
for SYNCH
end for;
end CFG_FD_SYNCH;

テストベンチのコードは

entity TBFD is
end TBFD;

architecture TEST of TBFD is

signal  CK:     std_logic :='0';
signal  RESET:      std_logic :='0';
signal  D:      std_logic :='0';
signal  QSYNCH:     std_logic;
signal  QASYNCH:    std_logic;

component FD

Port (  CK: In  std_logic;
    RESET:  In  std_logic;
    D:  In  std_logic;
    Q:  Out std_logic);
end component;

begin 

FD_SYNCH : FD
Port Map ( CK, RESET, D, QSYNCH); 

FD_ASYNCH : FD
Port Map ( CK, RESET, D, QASYNCH); 


RESET <= '0', '1' after 0.6 ns, '0' after 1.1 ns, '1' after 2.2 ns, '0' after 3.2 ns;   


D <= '0', '1' after 0.4 ns, '0' after 1.1 ns, '1' after 1.4 ns, '0' after 1.7 ns, '1' after        1.9 ns;


PCLOCK : process(CK)
begin
    CK <= not(CK) after 0.5 ns; 
end process;

end TEST;

configuration FDTEST of TBFD is
  for TEST

  for FD_SYNCH : FD
     use configuration WORK.CFG_FD_SYNCH; 
  end for;

  for FD_ASYNCH : FD
     use configuration WORK.CFG_FD_ASYNCH; 
  end for;

  end for;
end FDTEST;

問題はテストベンチ中です。同期部分の波形 ( QSYNCH 信号波) は常に非同期部分の波形 ( QASYNCH 信号波) と等しくなります。どうすればこの問題を解決できますか?