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私は t-bird ライト コントローラーに取り組んでいますが、コードでこれらのエラーが発生し続けています。コードを実行しても、実際には何も問題はありません。VHDLの経験はあまりありませんが、それが正しいか間違っているかはわかります。助けが必要です

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;

 entity tbird is
 PORT(clk, lts,rts,haz,brake: IN bit;
 lc,lb,la,ra,rb,rc: OUT bit);
 end tbird;

 architecture one of tbird is
 TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3,lr4);
 signal state ,next_state: state_type;
 BEGIN
 process 
 BEGIN
 WAIT UNTIL clk='1' AND clk'event;
 state <= next_state;
 end process;
 --next state generation
 PROCESS(state,rts,lts,haz,brake)
 begin
 case state is
 WHEN idle => 
 IF(haz='1' OR (lts='1' AND rts='1' AND break='0')) Then next_state <= lr3;
  elsif (haz ='0' AND lts='0' and brake='0' and rts='1') then next_state <= r1;
  elsif (haz ='0' and lts='1' and brake='0' and rts='0') then next_state <= l1;
  elsif (haz='0' and lts='0' and brake='1' and rts='0') then next_state <= lr4;
  else next_state <= idle;
  end if;

 WHEN l1=> IF(haz='1') THEN next_state <= lr3;
  elsif (brake='1') then next_state <= lr4;
  ELSE next_state <= l2;
  END IF;

 WHEN l2=> 
  IF(haz='1') THEN next_state<= lr3;
  elsif(brake ='1') then next_state <= lr4;
  ELSE next_state <= l3;
  END IF;

 WHEN l3=>
  next_state <=idle;

 WHEN r1=>IF(haz='1') THEN next_state <= lr3;
  elsif(brake='1') then next_state <= lr4;
  ELSE next_state <= r2;
  END IF;


 WHEN r2=>IF(haz='1') THEN next_state <= lr3;
  IF(brake='1') THEN next_state <= lr4;
  ELSE next_state <= r3;
  END IF;
  WHEN r3=> next_state <= idle;

  WHEN lr3=> next_state <= idle;
  WHEN lr4=>IF(brake='1')next_state <=lr4;
  else next_state <= idle;
  END case;
  END PROCESS;


 PROCESS(state)
 BEGIN
  case state is
  WHEN idle => lc<='0'; lb<='0'; la<='0';ra<='0'; rb <='0'; rc<='0';
  WHEN l1 => lc<='0'; lb<='0'; la<='1';ra<='0'; rb <='0'; rc<='0';
  WHEN l2 => lc<='0'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN l3 => lc<='1'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN r1 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='0'; rc<='0';
  WHEN r2 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='0';
  WHEN r3 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='1';
  WHEN lr3 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1'; 
  WHEN lr4 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1';
 END case;
 END PROCESS;
 END one;

これらはエラーです

 INFO:HDLCompiler:1061 - Parsing VHDL file "D:/ISE/DSD LABS/assigment/brake.vhd" into library work
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 53: Syntax error near "WHEN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 55: Syntax error near "WHEN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 56: Syntax error near "WHEN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 58: Syntax error near "case".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 63: Syntax error near "BEGIN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 75: Syntax error near "PROCESS".
 ERROR:ProjectMgmt - 6 error(s) found while parsing design hierarchy.
4

3 に答える 3

3

行で：WHEN lr4=>IF(brake='1')next_state <=lr4;

単語THENが欠落しています。

于 2014-12-15T15:12:38.787 に答える
0

エラー メッセージ Line numbers does not match your VHDL code example に注意してください。

VHDL サンプルの分析を妨げているもの:

architecture one of tbird is
 TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3,lr4);
 signal state ,next_state: state_type;
 BEGIN
 process 
 BEGIN
 WAIT UNTIL clk='1' AND clk'event;
 state <= next_state;
 end process;
 --next state generation
 PROCESS(state,rts,lts,haz,brake)
 begin
 case state is
 WHEN idle =>  -- brake NOT break
 IF(haz='1' OR (lts='1' AND rts='1' AND brake='0')) Then next_state <= lr3;
  elsif (haz ='0' AND lts='0' and brake='0' and rts='1') then next_state <= r1;
  elsif (haz ='0' and lts='1' and brake='0' and rts='0') then next_state <= l1;
  elsif (haz='0' and lts='0' and brake='1' and rts='0') then next_state <= lr4;
  else next_state <= idle;
  end if;

 WHEN l1=> IF(haz='1') THEN next_state <= lr3;
  elsif (brake='1') then next_state <= lr4;
  ELSE next_state <= l2;
  END IF;

 WHEN l2=> 
  IF(haz='1') THEN next_state<= lr3;
  elsif(brake ='1') then next_state <= lr4;
  ELSE next_state <= l3;
  END IF;

 WHEN l3=>
  next_state <=idle;

 WHEN r1=>IF(haz='1') THEN next_state <= lr3;
  elsif(brake='1') then next_state <= lr4;
  ELSE next_state <= r2;
  END IF;


 WHEN r2=>IF(haz='1') THEN next_state <= lr3;
  ELSIF(brake='1') THEN next_state <= lr4;  -- ELSIF was IF
  ELSE next_state <= r3;
  END IF;
  WHEN r3=> next_state <= idle;

  WHEN lr3=> next_state <= idle;
  WHEN lr4=>IF(brake='1')THEN next_state <=lr4; -- MISSING THEN
  else next_state <= idle;
  END IF;                       -- MISSING ENDIF
  END case;
  END PROCESS;


 PROCESS(state)
 BEGIN
  case state is
  WHEN idle => lc<='0'; lb<='0'; la<='0';ra<='0'; rb <='0'; rc<='0';
  WHEN l1 => lc<='0'; lb<='0'; la<='1';ra<='0'; rb <='0'; rc<='0';
  WHEN l2 => lc<='0'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN l3 => lc<='1'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN r1 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='0'; rc<='0';
  WHEN r2 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='0';
  WHEN r3 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='1';
  WHEN lr3 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1'; 
  WHEN lr4 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1';
 END case;
 END PROCESS;
 END one;

2 番目のプロセスの case ステートメントの選択でbreak代わりに使用しました。brakeidle

同じケース ステートメントを選択r2すると、2 番目のステートメントを にするつもりだったIFようELSIFです。

lr4同じ case ステートメントを選択するとTHEN、if ステートメントの代入の前に a がありません。

ENDIF同じ if ステートメントの for がありません。

また、コンテキスト句 (エンティティ宣言の前のライブラリおよび use ステートメント) が必要ないことにも注意してください。入力ポートと出力ポートはすべて BIT 型であり、他の宣言されたシグナルは type のみstate_typeです。

これは、コードを整形すると次のようになります。

-- library ieee;                  -- NOT NEEDED
-- use ieee.std_logic_1164.all;   -- NOT NEEDED
-- use ieee.std_logic_arith.all;  -- NOT NEEDED

 entity tbird is
     port (
         clk, lts,rts,haz,brake:    in  bit;
         lc,lb,la,ra,rb,rc:         out bit
     );
 end tbird;

 architecture prettified of tbird is
     type state_type is (idle,l1,l2,l3,r1,r2,r3,lr3,lr4);
     signal state, next_state: state_type;
 begin
STATE_REG:
     process 
     begin
         wait until clk = '1' and clk'event;
         state <= next_state;
     end process;
NEXTSTATE:
    process(state,rts,lts,haz,brake)
    begin
        case state is
            when idle => 
                 if haz = '1' or (lts = '1' and rts = '1' and brake = '0') then -- brake NOT break
                     next_state <= lr3;
                 elsif haz = '0' and lts ='0' and brake ='0' and rts = '1' then 
                     next_state <= r1;
                 elsif haz = '0' and lts = '1' and brake = '0' and rts = '0' then 
                     next_state <= l1;
                 elsif haz = '0' and lts = '0' and brake = '1' and rts = '0' then 
                     next_state <= lr4;
                 else
                     next_state <= idle;
                 end if;
            when l1 => 
                if haz = '1' then 
                    next_state <= lr3;
                elsif brake = '1' then 
                    next_state <= lr4;
                else 
                    next_state <= l2;
                end if;
            when l2 => 
                if haz='1' then 
                    next_state<= lr3;
                elsif brake ='1' then 
                    next_state <= lr4;
                else 
                    next_state <= l3;
                end if;
            when l3 =>
                next_state <=idle;
            when r1 =>
                if haz = '1' then 
                    next_state <= lr3;
                elsif brake = '1' then 
                    next_state <= lr4;
                else 
                    next_state <= r2;
                end if;
            when r2 =>
                if haz = '1' then 
                    next_state <= lr3;
                elsif brake = '1' then  -- WAS if looks like should be elsif
                    next_state <= lr4;
                else 
                    next_state <= r3;
                end if;
            when r3 => 
                next_state <= idle;
            when lr3 => 
                next_state <= idle;
            when lr4 => 
                if brake = '1' then       -- MISSING then
                    next_state <= lr4;
                else 
                    next_state <= idle;
                end if;                 -- MISSING endif
        end case;
    end process;
MOORE_OUTPUTS:    
    process(state)
    begin
        case state is
            when idle =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '0'; rb <= '0'; rc <= '0';
            when l1 =>
                lc <= '0'; lb <= '0'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0';
            when l2 =>
                lc <= '0'; lb <= '1'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0';
            when l3 =>
                lc <= '1'; lb <= '1'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0';
            when r1 =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '0'; rc <= '0';
            when r2 =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '1'; rc <= '0';
            when r3 =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '1'; rc <= '1';
            when lr3 =>
                lc <= '1'; lb <= '1'; la <= '1'; ra <= '1'; rb <= '1'; rc <= '1'; 
            when lr4 =>
                lc <= '1'; lb <= '1'; la <= '1'; ra <= '1'; rb <= '1'; rc <= '1';
        end case;
    end process;
end architecture;

ラベルを使用するという考えは、回りくどい方法で物事を指す必要がないようにし、空白とインデントを一貫して使用することでコードを読みやすくし、不要な括弧のペアを削除しました.

MOORE_OUTPUTSでインデックス付けされた定数配列を使用して、プロセスを別の方法で表現したくなるでしょうstate_type'pos(state)。よりコンパクトになり、変更も簡単になります。新しい宣言は、( の前の) プロセス ステートメントの宣言項目である可能性がありますbegin。

そのプロセスは次のようになります。

MOORE_OUTPUTS:
    process (state)
    type state_outputs is array (state_type'pos(idle) to state_type'pos(lr4)) 
        of bit_vector(0 to 5);
    constant outputs: state_outputs := ( 
                      -- lc   lb   la   ra   rb   rc
                        ('0', '0', '0', '0', '0', '0'), -- idle
                        ('0', '0', '1', '0', '0', '0'), -- l1
                        ('0', '1', '1', '0', '0', '0'), -- l2
                        ('1', '1', '1', '0', '0', '0'), -- l3
                        ('0', '0', '0', '1', '0', '0'), -- r1
                        ('0', '0', '0', '1', '1', '0'), -- r2
                        ('0', '0', '0', '1', '1', '1'), -- r3
                        ('1', '1', '1', '1', '1', '1'), -- lr3
                        ('1', '1', '1', '1', '1', '1')  -- lr4
                    ); 
    begin
        (lc, lb, la, ra, rb, rc) <= outputs(state_type'pos(state));
    end process;

これは、直接操作できる素敵なテーブルを提供します。

私は両方のアーキテクチャを分析して詳しく説明しましたが、どちらもシミュレートされていません。

于 2014-12-15T19:00:23.840 に答える
0

次のコードで、"break" を "brake" に名前変更します。エンティティで「ブレーキ」を宣言しました:

IF(haz='1' OR (lts='1' AND rts='1' AND break='0')) Then next_state <= lr3;

end if;次のコードでは、行末にステートメントを追加します。

WHEN r2=>IF(haz='1') THEN next_state <= lr3;

次のコードでは、適切な場所でthenandend if;ステートメントを使用しています。

WHEN lr4=>IF(brake='1')next_state <=lr4;
    else next_state <= idle;
END case;

上記の変更により、構文エラーは削除されます。

于 2014-12-15T16:35:16.993 に答える