vhdl - VHDL: エンティティ (コンポーネント) の結合に関する問題

Question

また私！

エンティティがどのように組み合わされるかを示すために、非常に単純なものを書きました。ただし、結合されたエンティティの出力が値 (U 以外) を想定しない理由を理解するのに苦労しています。コードは次のとおりです (非常にシンプルです。お約束します!)

library ieee;
use ieee.std_logic_1164.all;

entity OR_LOGIC is
    port(
        in_a  : in  std_logic;
        in_b  : in  std_logic;
        out_c : out std_logic
    );
end entity;

architecture OR_LOGIC_ARCH of OR_LOGIC is
begin
    out_c <= in_a or in_b;
end OR_LOGIC_ARCH;


library ieee;
use ieee.std_logic_1164.all;

entity AND_LOGIC is
    port(
        in_a  : in  std_logic;
        in_b  : in  std_logic;
        out_c : out std_logic
    );
end entity;

architecture AND_LOGIC_ARCH of AND_LOGIC is
begin
    out_c <= in_a and in_b;
end AND_LOGIC_ARCH;


library ieee;
use ieee.std_logic_1164.all;

entity COMBO is
    port(
        in_a  : in  std_logic;
        in_b  : in  std_logic;
        in_c  : in  std_logic;
        out_d : out std_logic
    );
end entity;

architecture COMBO_ARCH of COMBO is
    signal wire1 : std_logic;
    signal wire2 : std_logic;
    component OR_LOGIC
        port(
            in_a  : in  std_logic;
            in_b  : in  std_logic;
            out_c : out std_logic
        );
    end component;
    component AND_LOGIC
        port(
            in_a  : in  std_logic;
            in_b  : in  std_logic;
            out_c : out std_logic
        );
    end component;
begin

    or1 : OR_LOGIC port map (in_a, in_b, wire1);
    and1 : AND_LOGIC port map(in_c, wire1, wire2);
end COMBO_ARCH;

その後：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TEST_ENTITY is
end entity TEST_ENTITY;

architecture TEST_ENTITY_ARCH of TEST_ENTITY is    
    component ANDandOR
        port(
            in_a  : in  std_logic;
            in_b  : in  std_logic;
            in_c  : in  std_logic;
            out_d : out std_logic
        );
    end component; 
    signal in_a, in_b, in_c, out_d : std_logic;

begin

    combination : ANDandOR port map (in_a, in_b, in_c, out_d);

    process
    begin
        in_a <= '0';
        in_b <= '0';
        in_c <= '0';
        wait for 5ns;

        in_a <= '1';
        in_b <= '0';
        in_c <= '1';
        wait for 5ns;

        in_a <= '0';
        in_b <= '1';
        in_c <= '0';
        wait for 5ns;
    end process;

end architecture TEST_ENTITY_ARCH;