問題タブ [system-verilog-assertions]

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system-verilog - Systemverilog property implication with or (||) is not working as expected?

I am trying to write sytemverilog assertions for determining clock period(140MHz) with arbitrary + or - value of 0.001ns, here in this systemverilog property used "or" operator (||) for +/- deviations/changes of time periods but outputs are not as expected, can anyone explain what is the exact cause of this?, and for any value of clk_prd the assertion gets asserted which is not as expected, also please mention what is the optimal solution for this?

code snippet below,

Current output:

Expected output

(ref from link)

system-verilog system-verilog-assertions

2017-07-25T12:35:25.103

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問題タブ [system-verilog-assertions]

system-verilog - Systemverilog property implication with or (||) is not working as expected?

Reference