Xilinx XST、iSim、Altera Quartus II、Mentor Graphics QuestaSim、および GHDL 用のクロスプラットフォーム VHDL ライブラリを作成しました。これらのライブラリを使用する ISE 14.7 プロジェクトを Vivado 2014.4 に移植したいと考えましたが、1 つのライブラリに致命的な問題があるようです。
私のライブラリでphysicalは、次のようないくつかの新しいユーザー定義の物理型が定義されFREQUENCYていBAUDます。変換機能とレポート機能。
主な使用例の 1 つは、特定の遅延とシステム周波数に対する遅延またはカウンター サイクルの計算です。たとえば、125 ns の遅延には、100 MHz で 12 または 13 の遅延サイクルが必要です (これは、.5 での丸めモードによって異なります)。
Vivado Synth からいくつかの情報と警告が表示されます (一部は assert ステートメントの結果です。以下の最小限の例を参照してください)。
[Synth 8-638] synthesizing module 'Top_PhysicalTest' ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":410]
[Synth 8-63] RTL assertion: "to_time: f= 2147483647.1000 THz return 2147483647.1000 sec" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":277]
[Synth 8-63] RTL assertion: "res_real: 0.000000" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":321]
[Synth 8-63] RTL assertion: "TimingToCycles:
Timing: 2147483647.1000 sec
Clock_Period: 2147483647.1000 sec
RoundingStyle: TO_NEAREST
res_real = 2147483647.1000
=> 0" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":323]
[Synth 8-26] 'image of non-integer, non-enum type not implemented ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":422]
[Synth 8-63] RTL assertion: "CLOCK_FREQ: <complex-type>" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":422]
[Synth 8-63] RTL assertion: "CLOCK_FREQ: 2147483647.1000 THz" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":423]
[Synth 8-26] 'image of non-integer, non-enum type not implemented ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":424]
[Synth 8-63] RTL assertion: "DELAY: <complex-type>" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":424]
[Synth 8-63] RTL assertion: "DELAY: 2147483647.1000 sec" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":425]
[Synth 8-63] RTL assertion: "CYCLES: 0" ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":426]
[Synth 8-256] done synthesizing module 'Top_PhysicalTest' (1#1) ["D:/Temp/PhysicalTest_Vivado2014.4/vhdl/Top_PhysicalTest.vhd":410]
[Synth 8-3330] design Top_PhysicalTest has an empty top module
[Synth 8-3331] design Top_PhysicalTest has unconnected port Clock
[Synth 8-3330] design Top_PhysicalTest has an empty top module
[Synth 8-3331] design Top_PhysicalTest has unconnected port Clock
[Project 1-571] Translating synthesized netlist
私のシナリオは少し複雑なので、最小限の例は本来あるべきほど最小限に見えません。コピー/置換エラーを防ぐためにすべての関数をインライン化したわけではなく、デバッグおよびアサート/レポート ルーチンを削除しませんでした。
概要：
- パッケージ utils: 一般的な型、列挙型、および関数
- パッケージ文字列: 文字列操作および変換関数
- パッケージの物理的: 新しいタイプとその機能
- エンティティ: 単純な遅延要素/シフト レジスタを実装する単一の最上位エンティティ
最小限の例:
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package utils is
-- rounding style
type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN);
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING;
function imin(arg1 : integer; arg2 : integer) return integer;
function imax(arg1 : integer; arg2 : integer) return integer;
function log2ceil(arg : positive) return natural;
function log2ceilnz(arg : positive) return positive;
end package utils;
package body utils is
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function imin(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 < arg2 then return arg1; end if;
return arg2;
end function;
function imax(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 > arg2 then return arg1; end if;
return arg2;
end function;
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
function log2ceilnz(arg : positive) return positive is
begin
return imax(1, log2ceil(arg));
end function;
end utils;
-- ============================================================================
-- Package: String related functions and types
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use work.utils.all;
package strings is
function raw_format_nat_dec(value : NATURAL) return STRING;
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
FUNCTION resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := NUL) RETURN STRING;
function str_length(str : STRING) return NATURAL;
function str_trim(str : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
end package strings;
package body strings is
-- raw_format_* functions
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant int : INTEGER := integer((value * s) - 0.5); -- force ROUND_DOWN
constant frac : INTEGER := integer((((value * s) - real(int)) * 10.0**precision) - 0.5); -- force ROUND_DOWN
constant res : STRING := raw_format_nat_dec(int) & "." & raw_format_nat_dec(frac);
begin
-- assert (not MY_VERBOSE)
-- report "str_format:" & CR &
-- " value:" & REAL'image(value) & CR &
-- " int = " & INTEGER'image(int) & CR &
-- " frac = " & INTEGER'image(frac)
-- severity note;
return ite((s < 0.0), "-" & res, res);
end function;
-- resize
FUNCTION resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := NUL) RETURN STRING IS
CONSTANT MaxLength : NATURAL := imin(size, str'length);
VARIABLE Result : STRING(1 TO size) := (OTHERS => FillChar);
BEGIN
if (MaxLength > 0) then
Result(1 TO MaxLength) := str(str'low TO str'low + MaxLength - 1);
end if;
RETURN Result;
END FUNCTION;
-- String functions
FUNCTION str_length(str : STRING) RETURN NATURAL IS
VARIABLE l : NATURAL := 0;
BEGIN
FOR I IN str'range LOOP
IF (str(I) = NUL) THEN
RETURN l;
ELSE
l := l + 1;
END IF;
END LOOP;
RETURN str'length;
END FUNCTION;
function str_trim(str : STRING) return STRING is
constant len : NATURAL := str_length(str);
begin
if (len = 0) then
return "";
else
return resize(str, len);
end if;
end function;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
end strings;
-- ============================================================================
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Authors: Patrick Lehmann
--
-- ============================================================================
library IEEE;
use IEEE.MATH_REAL.all;
use work.utils.all;
use work.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
THz = 1000 GHz;
end units;
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
function to_time(f : FREQ) return TIME;
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return NATURAL;
function to_string(t : TIME; precision : NATURAL := 3) return STRING;
function to_string(f : FREQ; precision : NATURAL := 3) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation by default (fs values are converted to 0 ps)
-- activate fs support by overriding the time precision
-- fuse[.exe] [...] -timeprecision_vhdl 1fs [...]
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
begin
if (a < 1 us) then
return real(a / MTRIS) / real(b / MTRIS);
elsif (a < 1 ms) then
return real(a / (1000 * MTRIS)) / real(b / MTRIS) * 1000.0;
elsif (a < 1 sec) then
return real(a / (1000000 * MTRIS)) / real(b / MTRIS) * 1000000.0;
else
return real(a / (1000000000 * MTRIS)) / real(b / MTRIS) * 1000000000.0;
end if;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
-- conversion functions
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
if (f < 1.0 kHz) then res := div(1.0 Hz, f) * 1.0 sec;
elsif (f < 1.0 MHz) then res := div(1.0 kHz, f) * 1.0 ms;
elsif (f < 1.0 GHz) then res := div(1.0 MHz, f) * 1.0 us;
elsif (f < 1.0 THz) then res := div(1.0 GHz, f) * 1.0 ns;
else res := div(1.0 THz, f) * 1.0 ps;
end if;
assert FALSE report "to_time: f= " & to_string(f) & " return " & to_string(res) severity note;
return res;
end function;
-- convert physical types (TIME, FREQ) to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1.0 fs) then return div(t, 1.0 fs);
elsif (scale = 1.0 ps) then return div(t, 1.0 ps);
elsif (scale = 1.0 ns) then return div(t, 1.0 ns);
elsif (scale = 1.0 us) then return div(t, 1.0 us);
elsif (scale = 1.0 ms) then return div(t, 1.0 ms);
elsif (scale = 1.0 sec) then return div(t, 1.0 sec);
else report "to_real: scale must have a value of '1.0 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1.0 Hz) then return div(f, 1.0 Hz);
elsif (scale = 1.0 kHz) then return div(f, 1.0 kHz);
elsif (scale = 1.0 MHz) then return div(f, 1.0 MHz);
elsif (scale = 1.0 GHz) then return div(f, 1.0 GHz);
elsif (scale = 1.0 THz) then return div(f, 1.0 THz);
else report "to_real: scale must have a value of '1.0 <unit>'" severity failure;
end if;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(res_real + 0.5);
when ROUND_DOWN => res_nat := natural(res_real);
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
report "res_real: " & REAL'image(res_real) severity note;
assert FALSE
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing) & CR &
" Clock_Period: " & to_string(Clock_Period) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL := 3) return STRING is
variable unit : STRING(1 to 3) := (others => NUL);
variable value : REAL;
begin
if (t < 1.0 ps) then
unit(1 to 2) := "fs";
value := to_real(t, 1.0 fs);
elsif (t < 1.0 ns) then
unit(1 to 2) := "ps";
value := to_real(t, 1.0 ps);
elsif (t < 1.0 us) then
unit(1 to 2) := "ns";
value := to_real(t, 1.0 ns);
elsif (t < 1.0 ms) then
unit(1 to 2) := "us";
value := to_real(t, 1.0 us);
elsif (t < 1.0 sec) then
unit(1 to 2) := "ms";
value := to_real(t, 1.0 ms);
else
unit := "sec";
value := to_real(t, 1.0 sec);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(f : FREQ; precision : NATURAL := 3) return STRING is
variable unit : STRING(1 to 3) := (others => NUL);
variable value : REAL;
begin
if (f < 1.0 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1.0 Hz);
elsif (f < 1.0 MHz) then
unit := "kHz";
value := to_real(f, 1.0 kHz);
elsif (f < 1.0 GHz) then
unit := "MHz";
value := to_real(f, 1.0 MHz);
elsif (f < 1.0 THz) then
unit := "GHz";
value := to_real(f, 1.0 GHz);
else
unit := "THz";
value := to_real(f, 1.0 THz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.utils.all;
use work.strings.all;
use work.physical.all;
entity Top_PhysicalTest is
Port (
Clock : in STD_LOGIC;
Input : in STD_LOGIC;
Output : out STD_LOGIC
);
end;
architecture rtl of Top_PhysicalTest is
-- configuration
constant CLOCK_FREQ : FREQ := 100 MHz;
constant SHIFTER_DELAY : TIME := 125 ns;
-- calculations
constant SHIFTER_DELAY_CYCLES : NATURAL := TimingToCycles(SHIFTER_DELAY, CLOCK_FREQ);
constant SHIFTER_BITS : NATURAL := SHIFTER_DELAY_CYCLES + 2; -- to prevent an underrun, while Vivado has a bug
signal Shifter_nxt : STD_LOGIC_VECTOR(SHIFTER_BITS - 1 downto 0);
signal Shifter_d : STD_LOGIC_VECTOR(SHIFTER_BITS - 2 downto 0) := (others => '0');
begin
assert false report "CLOCK_FREQ: " & FREQ'image(CLOCK_FREQ) severity note;
assert false report "CLOCK_FREQ: " & to_string(CLOCK_FREQ) severity note;
assert false report "DELAY: " & TIME'image(SHIFTER_DELAY) severity note;
assert false report "DELAY: " & to_string(SHIFTER_DELAY) severity note;
assert false report "CYCLES: " & INTEGER'image(SHIFTER_DELAY_CYCLES) severity note;
Shifter_nxt <= Shifter_d & Input;
Shifter_d <= Shifter_nxt(Shifter_d'range) when rising_edge(Clock);
Output <= Shifter_nxt(SHIFTER_DELAY_CYCLES);
end;
UDPT ::= ユーザー定義の物理タイプ
私の観察：
- 合成はエラーなしで実行されますが、誤った計算が発生します
- 'イメージは実装されていません -> これをどのようにデバッグする必要がありますか?
- INTEGER'high の値を保持しているようです
質問:
- Vivado でこれを修正する方法を教えてください。
- 誰でもこの動作を確認できますか?
- 物理型を導入した VHDL 標準 (87、93、...) はどれですか?
注意: 質問を CR から SO に手動で移動してください。
編集1：
エラーを次のように削除しました。
- 物理型の 10 進リテラルは false で処理されます -> 結果は常に 0 です
- 物理型の属性
'image(..)はもう実装されていません - 物理タイプを含む操作。比較は偽の値になります
- 物理型の値の範囲は単調ではありません
この問題はザイリンクス フォーラムで報告されています。