ラップトップに VHDL シミュレータがインストールされていないため、EDA プレイグラウンドを使用して次の VHDL コードを実行しようとしています。上がソースコード、下がテストベンチです。ただし、解決する必要があるいくつかのエラーが発生しています。エラーを以下に示します。問題を解決するのを手伝ってくれる人はいますか? 前もって感謝します。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity led_controller is
Port ( clk, reset: in std_logic;
in_word: in std_logic_vector(7 downto 0);
LEDs: out std_logic_vector(3 downto 0));
end led_controller;
architecture behavior of led_controller is
--------------------- signals ---------------------
type freq is array (0 to 3) of integer range 0 to 50000;
signal frq: freq := (25000, 10000, 5000, 2500);
signal led_freq_count: integer range 0 to 50000 := frq(0);
type d is array (0 to 3) of integer range 0 to 100;
signal duty: d := (10, 30, 60, 85);
signal duty_cycle: integer range 0 to 100 := duty(0);
signal LED_switch, new_command: std_logic := '0';
begin
--------- clock process / sync reset configuration ---------------
process (clk)
variable duty_counter: integer range 0 to 100 := 100;
variable freq_counter: integer range 0 to 50000 := led_freq_count;
begin
if rising_edge(clk) then
------- if reset was high or new in_word were arrived --------
if reset = '1' or new_command = '1' then
LEDs <= "0000";
duty_counter := 100;
freq_counter := led_freq_count;
new_command <= '0';
else
------- blinking process --------
if freq_counter = 0 then
freq_counter := led_freq_count;
LED_switch <= not LED_switch;
else
freq_counter := freq_counter - 1;
end if;
if duty_counter = 0 then
duty_counter := 100;
else
duty_counter := duty_counter - 1;
end if;
------ output assignment -------
if LED_switch = '1' and duty_counter < duty_cycle then
LEDs <= "1111";
else
LEDs <= "0000";
end if;
end if;
end if;
end process;
--------- input process---------------
process (in_word)
begin
case in_word(3 downto 0) is
when "0001" => led_freq_count <= frq(0);
when "0010" => led_freq_count <= frq(1);
when "0100" => led_freq_count <= frq(2);
when "1000" => led_freq_count <= frq(3);
when others => led_freq_count <= frq(0);
end case;
case in_word(7 downto 4) is
when "0001" => duty_cycle <= duty(0);
when "0010" => duty_cycle <= duty(1);
when "0100" => duty_cycle <= duty(2);
when "1000" => duty_cycle <= duty(3);
when others => duty_cycle <= duty(0);
end case;
new_command <= '1';
end process;
end behavior;
テストベンチ.vhd:
initial begin
$dumpfile("dump.vcd");
$dumpvars;
#10000 $finish;
end
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main_testbench is
end main_testbench;
architecture behavior of main_testbench is
component led_controller is
Port ( clk, reset: in std_logic; -- system clock is assumed 10KHz
in_word: in std_logic_vector(7 downto 0); -- LS 4 bits - frequency & MS 4 bits - duty-cycle
LEDs: out std_logic_vector(3 downto 0));
end component;
signal clk, reset: std_logic := '0';
signal in_word: std_logic_vector(7 downto 0) := "00010001"; -- 0.2 Hz, 10% duty cycle
signal LEDs: std_logic_vector(3 downto 0) := "0000";
type in_word_commands is array (0 to 15) of std_logic_vector(7 downto 0);
signal in_words: in_word_commands := ("00010001", "00010010", "00010100", "00011000", -- 10% duty cycle with 0.2Hz, 0.5Hz, 1Hz, 2Hz
"00100001", "00100010", "00100100", "00101000", -- 30% duty cycle with 0.2Hz, 0.5Hz, 1Hz, 2Hz
"01000001", "01000010", "01000100", "01001000", -- 60% duty cycle with 0.2Hz, 0.5Hz, 1Hz, 2Hz
"10000001", "10000010", "10000100", "10001000"); -- 85% duty cycle with 0.2Hz, 0.5Hz, 1Hz, 2Hz
signal command_num : integer := 0;
begin
dut: led_controller port map (clk, reset, in_word, LEDs);
clk <= not clk after 50 us; -- 0.1ms/2 = 50us
command_num <= 0 after 5000 ms when command_num = in_words'HIGH else command_num + 1 after 5000 ms;
in_word <= in_words(command_num);
end behavior;
[2018-05-13 10:40:56 EDT] vlib work && vcom '-2008' design.vhd testbench.vhd && vsim -c -do "vsim testbench; vcd file dump.vcd; vcd add -r sim:/ testbench /*; run 80000 ms; exit"
VSIMSA: 構成ファイルが変更されました:/home/runner/library.cfg
ALIB: ライブラリworkが接続されました。work = /home/runner/work/work.lib
Aldec, Inc. VHDL Compiler, build 2014.06.88
VLM 初期化パス: "/home/runner/library.cfg".
DAGGEN WARNING DAGGEN_0523: "ソースは -dbg スイッチなしでコンパイルされています。行ブレークポイントとアサーション デバッグは利用できません。"
COMP96 ファイル: design.vhd COMP96 Compile Entity "led_controller"
COMP96 Compile Architecture "behavior" of Entity "led_controller"
COMP96 ERROR COMP96_0016: "設計単位の宣言が必要です。" "testbench.vhd" 1 1
COMP96 Compile Entity "main_testbench"
COMP96 Compile Architecture "behavior" of Entity "main_testbench"
COMP96 Compile failure 1 Errors 0 Warnings Analysis time : 40.0 [ms]
予期される終了コード: 0、受信: 1